Paper Details

Reference:

Robin Grindley, Tarek S. Abdelrahman, Stephen D. Brown, Steve Caranci, Derek DeVries, Benjamin Gamsa, Alexander Grbic, Mitch Gusat, Robert Ho, Orran Krieger, Guy G. Lemieux, Kelvin Lovless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, and Zeljko Zilic,
"The NUMAchine multiprocessor",
In Proceedings International Conference on Parallel Processing (ICPP'00), Toronto ON, Canada, IEEE Computer Society, Washington, DC, USA, August, 2000, pp. 487–496.

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Abstract:

Small-scale multiprocessors are becoming increasingly economical and common, whereas larger multiprocessors continue to have higher per-node costs. The NUMAchine multiprocessor project seeks to make large-scale multiprocessors more economical while maintaining high performance by exploring architectural and hardware features for low-cost, modular multiprocessors. To demonstrate our approach, we have implemented a prototype system that is scalable to 128 processors. An efficient directory-based cache coherence protocol exploits our hierarchical ring-based interconnect and supports sequential consistency. This paper documents the design choices and the resulting performance of the system using both simulation results and measurements on the prototype hardware.

Keywords:

Computer architecture, shared-memory multiprocessor, hierarchical rings, cache coherence protocols, scalability

Reference Info:

DOI: 10.1109/ICPP.2000.876165
ACMid: 852940
ISBN: 0-7695-0768-9

BibTeX:

@inproceedings(Grindley-ICPP00,
    author = {Robin Grindley and Tarek S. Abdelrahman and Stephen D. Brown and Steve Caranci and Derek DeVries and Benjamin Gamsa and Alexander Grbic and Mitch Gusat and Robert Ho and Orran Krieger and Guy G. Lemieux and Kelvin Lovless and Naraig Manjikian and P. McHardy and Sinisa Srbljic and Michael Stumm and Zvonko G. Vranesic and Zeljko Zilic},
    title = {The {NUMAchine} multiprocessor},
    booktitle = {Proceedings International Conference on Parallel Processing (\textbf{ICPP'00})},
    location = {Toronto ON, Canada},
    publisher = {IEEE Computer Society},
    address = {Washington, DC, USA},
    month = {August},
    year = {2000},
    pages = {487-496},
    doi = {10.1109/ICPP.2000.876165},
    isbn = {0-7695-0768-9},
    keywords = {Computer architecture, shared-memory multiprocessor, hierarchical rings, cache coherence protocols, scalability}
)